Method for interconnecting magnetoresistive memory bits

ABSTRACT

A process of forming electrical interconnects between memory bits in a magnetoresistive memory device. A dielectric layer is formed to overlie a semiconductor substrate. A magnetoresistive storage layer is formed over the dielectric layer. An electrically conductive stop layer that is selective to etch processes and is mechanically hard is deposited over the magnetoresistive layer. A hardmask layer is formed to overlie the stop layer. The hardmask layer is etched to expose the stop layer. The stop layer and the magnetoresistive layer are etched using ion milling until the initial dielectric layer is exposed, defining individual magnetoresistive memory bits. A dielectric layer is formed over the hardmask layer and in the etch regions between magnetoresistive bits. The dielectric layer is planarized using chemical mechanical polish (CMP) until the stop layer is exposed. An interconnect layer is then formed over the exposed regions of the stop layer and is etched to form electrical interconnects between memory bits.

BACKGROUND OF THE INVENTION

[0001] Integrated circuits commonly use multilevel interconnections as ameans for electrically interconnecting semiconductor devices whichinclude active or passive circuit elements. High-density integratedcircuits such as Dynamic Random Access Memories (DRAMs) or Static RandomAccess Memories (SRAMs) are typically comprised of hundreds of thousandsor millions of semiconductor devices on a silicon substrate. These highdensity integrated circuits can be manufactured using a ComplementaryMetal-Oxide Semiconductor (CMOS) process and typically involve the useof multiple layers of vertically stacked metal interconnects.Fabrication of CMOS integrated circuits typically involves manymanufacturing steps which include repeated deposition or growth,patterning, and etching of thin films of semiconductor, polysilicon,metal, and dielectric materials to form the electrical circuitry whichtypically consists of n-channel and p-channel transistors and active andpassive circuit elements. Typically the steps to form the n-channel andp-channel transistors are completed before the interconnect metal isformed. While active and passive circuit elements may be fabricated atany time during the processing sequence depending on the particular typeof element, active circuit elements such as magnetoresistive memorystorage bits are typically fabricated at the third metal level after then-channel and p-channel transistors are formed.

[0002] Forming metal interconnect typically requires the repeated stepsof deposition or growth, patterning, and etching of metal, via anddielectric layers as necessary to connect the integrated circuitelements. Typically after the n-channel and p-channel transistors havebeen patterned and etched, a dielectric layer (e.g., silicon oxide) isformed over the surface of the topography to provide dielectricisolation between the devices and the overlying interconnect conductingregions. Next a contact layer is next patterned into the dielectriclayer to define openings in the dielectric layer where ohmic contactswill interconnect a first level of metal to the source, drain and gateregions of the n-channel and p-channel transistors. The contact layerpatterning is accomplished by first depositing a photoresist layer overthe dielectric layer. The photoresist is next selectively exposed tolight through a patterned reticle having the desired layer pattern.After exposure, the photoresist is developed to form a resist mask forthe desired layer pattern. The exposed layer is then etched to definethe contact openings. The last step is to deposit and etch the contactmetal.

[0003] Following the above process, the first level of metal isdeposited, patterned and etched over the contact and dielectric layers.The first level of metal is positioned over the contacts to provideelectrical interconnection between the first level of metal and then-channel and p-channel devices. A second dielectric layer is nextformed over the patterned first metal layer. After via holes are formedin the second dielectric layer to provide openings to the first metallayer, a conductive material, such as tungsten, is deposited to fill thevia holes and form “tungsten plugs.” After the tungsten plugs areformed, a second metal layer is deposited, patterned and etched over thetungsten plugs and the first dielectric layer. The second layer of metalis positioned over and in physical contact with the tungsten plugs toprovide electrical interconnection between the second layer of metal andthe first layer of metal. The steps of deposition or growth, patterning,and etching of metal, via and dielectric layers is repeated as desiredto provide the necessary interconnect to form the integrated circuit.

[0004] Magnetoresistive memory storage bits are typically fabricated atthe third metal level stage because the ferromagnetic materials used toform the magnetoresistive memory storage bits require processing below300 degrees C. The bits are developed through repeated deposition ofmultiple thin films which may include cobalt, copper, nickel, iron, ortantalum. Once the magnetoresistive bits are formed, the bits aretypically interconnected as a series of “bit strings”, where each bitstring may consist of 4, 8, or 16 bits. Each bit string is theninterconnected through metal interconnect layers to the electricalcircuits.

[0005] As successive metal interconnect layers are fabricated tointerconnect magnetoresistive bits, smooth planar surfaces becomeincreasingly difficult to maintain. The resulting uneven topographiescreate a variety of problems, all of which reduce integrated circuitfunctional yields and reliability. One problem that results is thatphotoresist material cannot be applied in a uniform fashion over uneventopographies. Thus when the steps of patterning the photoresist to forma resist mask and etching the exposed layer occur, features of theexposed layer may not be completely etched due to the incompletedevelopment of the photoresist.

[0006] Another problem that results is poor step coverage. Step coverageis defined as a measure of how well a metal or dielectric film conformsover a previous step and is represented by the ratio of the minimumthickness of a film as it crosses a step to the nominal thickness of thefilm over relatively flat horizontal regions. If the step coverage istoo small in metal films, high current densities can result which cancause electromigration or high current-induced stress failure. Smallstep coverages also increase metal interconnect layer resistance whichcan decrease integrated circuit performance or result in total failure.

[0007] Still another problem that can occur after etching the dielectriclayer to form the via holes is polymer residue damage to the via holes.After the via holes are etched, polymer residues which occur during theetching process can remain in the via hole resulting in poor contactresistance between the via fill metal and metal interconnect layer.

[0008] Yet another problem that can occur is oxidation of the via fillor metal interconnect layer material surfaces. After the via holes areetched and the tungsten fill metal is conformally deposited over thesurface of the via-level dielectric layer, the tungsten is etched backor chemical mechanically polished back to the surface of the dielectriclayer thus exposing the surface of the vias to oxidation.

[0009] Still yet another problem that can occur from the steps ofpatterning dielectric, via and metal layers is damage to underlyingmetal layers and film layers such as magnetoresistive thin film storagelayers. To prevent this damage, an additional electrically conductivelayer called a stop layer that is both chemically inert and physicallyhard must be formed to overlie the metal or film layers.

[0010] It is therefore an object of the present invention to provide amethod for forming metal to metal interconnects which have high-currentcarrying capability and which are electromigration resistant.

[0011] It is another object of the present invention to provide a methodfor forming interlevel metal to metal interconnects which reduce thenumber of processing steps required by eliminating one or more levels ofvia photolithography and etch processing steps.

[0012] It is yet another object of the present invention to provide amethod for forming interlevel metal to metal interconnects that providesmooth planar topographies and improved step coverage resulting inimproved reliability and yield.

[0013] It is still yet another object of the present invention toprovide a stop layer which prevents damage to underlying metalinterconnect layers or magnetoresistive thin film storage layers bybeing both chemically inert and physically hard resulting in improvedreliability and yield.

SUMMARY OF THE INVENTION

[0014] The present invention overcomes many of the disadvantages of theprior art by providing a method for manufacturing a high current,electromigration resistant interconnect for a magnetoresistive memory.Additional features and advantages of the invention will be set forth inthe description that follows, and will be apparent from the descriptionor will be learned through practice of the invention.

[0015] Although the preferred embodiment is used to interconnectmagnetoresistive elements, the method may also be used to connect othercircuit elements.

[0016] In a preferred embodiment of the present invention, an initialdielectric layer is formed to overlie a semiconductor substrate. Nextthe initial dielectric layer is planarized using a chemical mechanicalpolish. A magnetoresistive storage layer is then formed to overlie theinitial dielectric layer. The magnetoresistive storage layer may becomprised of a variety of magnetic materials including materials used toform Anisotropic Magnetoresistance (AMR) devices, GiantMagnetoresistance (GMR) devices, Colossal Magnetoresistance (CMR)devices, Tunneling Magnetoresistance (TMR) devices, ExtraordinaryMagnetoresistance (EMR) devices or Very Large Magnetoresistance (VLMR)devices. In a preferred embodiment, the magnetoresistive storage layeris formed of materials which form “pseudo” spin valve structures. Nextan initial stop layer is formed to overlie the magnetoresistive storagelayer. A final stop layer is then formed to overlie the initial stoplayer. A hardmask layer is next formed to overlie the final stop layer.The hardmask layer and the final stop layer are etched until the initialstop layer is exposed to define an etch region. Using the etch region asan etch opening, the initial stop layer and the magnetoresistive storagelayer are etched using blanket ion milling until the initial dielectriclayer is exposed to define two or more magnetoresistive memory storagebits. An isolation layer having sufficient thickness to fill in the gapscreated by etching the etch region is formed over the hardmask layer andin the etch region. The isolation layer is planarized using a chemicalmechanical polish until regions of the final stop layer are exposed. Theinterconnect layer is then formed over the exposed regions of the finalstop layer and is patterned and etched to electrically interconnect atleast two magnetoresistive memory storage bits.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other objects of the present invention and many of the attendantadvantages of the present invention will be readily appreciated as thesame becomes better understood by reference to the following detaileddescription when considered in connection with the accompanyingdrawings, in which like reference numerals designate like partsthroughout the figures thereof and wherein:

[0018] FIGS. 1-8 are cross-sectional views which illustrate sequentiallythe magnetoresistive memory interconnect fabrication method according tothe present invention;

[0019]FIG. 9 is a cross-section diagram illustrating a singlemagnetoresistive memory storage bit; and

[0020]FIG. 10 is a diagram illustrating the read and write controlcircuitry coupled to an array of magnetoresistive memory storage bits.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Referring now to the drawings, FIGS. 1-8 are cross-sectionalviews that illustrate sequentially the magnetoresistive memoryinterconnect fabrication method.

[0022]FIG. 1 is cross-sectional view showing initial dielectric layer 14deposited to overlie a semiconductor substrate 12. It is possible formany types of materials or structures to be formed on substrate 12 priorto forming initial dielectric layer 14, including contact, via orinterconnect metallization layers, CMOS integrated circuits, or activeor passive circuit elements. Fabrication of CMOS integrated circuitstypically involves the repeated deposition or growth, patterning, andetching of semiconductor, polysilicon, metal, or dielectric materials toform electrical circuitry which may include n-channel and p-channeltransistors. These transistors, along with the contact, via orinterconnect metallization layers, may form complex circuit functionswhich are required to operate a magnetoresistive memory and further mayinclude such functions as read and write control. The exact compositionof the materials or structures formed on substrate 12 does not directlyaffect the practice of the present invention.

[0023] Initial dielectric layer 14 is a dielectric material such assilicon nitride which is deposited on the surface of substrate 12.Dielectric layer 14 is planarized using a chemical mechanical polish toa degree of flatness which is sufficient for magnetoresistive layer 16.Once planarized, dielectric layer 14 provides the uniform surfacerequired by the very thin films used to form magnetoresistive layer 16.

[0024]FIG. 2 is a cross-sectional view showing magnetoresistive layer 16formed over the planarized surface of dielectric layer 14. The exactcomposition of magnetoresistive layer 16 does not directly affect thepractice of the present invention, but may include any materials havingthe property wherein a change in resistance of the material is observedwhen an external magnetic field is applied. In exemplary embodiments,these materials may include AMR materials, GMR materials, CMR materials,TMR materials, EMR materials, and VLMR materials.

[0025]FIG. 3 is a cross-sectional view showing initial stop layer 18,final stop layer 20 and hardmask layer 22 formed over themagnetoresistive layer 16. The exact composition of initial stop layer18 does not directly affect the practice of the present invention,except that it must be electrically conductive. The initial stop layer18 may include any materials having an etch selectivity which is greaterthan the etch selectivity of the hardmask layer 22 and final stop layer20. In exemplary embodiments, these materials may include chromium andsilicon.

[0026] The final stop layer 20 is deposited to overlie initial stoplayer 18. The exact composition of final stop layer 20 does not directlyaffect the practice of the present invention, but may include anymaterials that are electrically conductive, inert to chemicals containedin polishing slurries, and having a chemical mechanical polishselectivity which is greater than the chemical mechanical polishselectivity of the hardmask layer 20. In exemplary embodiments, thesematerials may include titanium and tungsten.

[0027] The hardmask layer 22 is deposited to overlie final stop layer20. The exact composition of hardmask layer 22 does not directly affectthe practice of the present invention. In exemplary embodiments, thismaterial may be silicon dioxide.

[0028]FIG. 4 is a cross-sectional view showing hardmask layer 22 andfinal stop layer 20 having been etched until the initial stop layer 18is exposed to define an etch region. The etch region is shown as thespace between hardmask layers 22 a and 22 b and the space between finalstop layers 20 a and 20 b.

[0029]FIG. 5 is a cross-sectional view showing initial stop layer 18 andmagnetoresistive layer 16 having been etched through using blanket ionmilling to expose the initial dielectric layer. The etch region is shownas the space between initial stop layer 18 a and 18 b andmagnetoresistive layer 16 a and 16 b.

[0030] Initial isolation layer 24 is deposited to overlie the hardmasklayer and the plurality of etch regions defined by blanket ion milling.

[0031]FIG. 6 is a cross-sectional view showing the final isolation layer26 deposited to overlie initial isolation layer 24. The thickness of thefinal isolation layer 26 must be great enough to fill any gaps createdby etching the etch region.

[0032]FIG. 7 is a cross-sectional view showing the structure afterchemical mechanical polishing. Isolation layers 26 and 24 and hardmasklayer 22 have been polished to expose final stop layers 20 a and 20 b.Isolation layers 26 and 24 films remain in the etch region. The chemicalmechanical polishing has been stopped by final stop layers 20 a and 20b.

[0033]FIG. 8 is a cross-sectional view showing the structure afterinterconnect layer 28 has been deposited to overlie final stop layers 20a and 20 b, initial isolation layer 24 and final isolation layer 26.Interconnect layer 28 has been etched to form a plurality ofinterconnect regions which connect each of the plurality ofmagnetoresistive elements to each other. The actual composition of theinterconnect layer does not directly affect the practice of the presentdevice, but may include any materials which provide a conductiveinterconnect between the magnetoresistive elements.

[0034] The chemical mechanical polishing process, as illustrated in FIG.7, eliminates the need for formation of vias by creating an opening inthe interlayer dielectric that allows for contact between initial andfinal metal layers. In so doing, the process described providessolutions to the problems associated with the formation of metal tometal interconnect vias that were described above.

[0035] Specifically, since the process is performed by polishing, largetopographies from previously patterned layers are planarized, therebyallowing interconnect layer 28 to be deposited over a planar surface.This reduces the step height of the interconnect to zero, thus insuring100% step coverage of interconnect layer 28 over final stop layers 20 aand 20 b. With full step coverage, the metal to metal interconnect thatis formed will have high-current carrying capability and beelectromigration resistant.

[0036] Yet another advantage realized by forming metal to metalinterconnects using a polishing process is a reduction in the number ofprocessing steps that result from eliminating one or more levels of viaphotolithography and etch processing steps. By eliminating these steps,processing issues associated with the formation of vias, such as polymerresidue damage in the via holes and damage to underlyingmagnetoresistive thin film storage layers, can be avoided.

[0037]FIG. 9 is a cross-sectional diagram showing one of a plurality ofembodiments of a magnetoresistive storage bit. The figure illustratesthe generalized components of magnetoresistance layer 16, which iscomposed of dual magnetic layers 30 a and 30 b and a coupling layer 30c.

[0038]FIG. 10 is a figure illustrating the read and write controlcircuitry coupled to an array of magnetoresistive memory storage bits 36a. The plurality of magnetoresistive storage bits 36 a are connected bythe plurality of interconnects 36 b to form a bit string 36. The addressof the memory location is determined by selection of both the word line32 and the bit string 36.

[0039] The present invention may be embodied in other specific formswithout departing from the spirit or essential attributes thereof, andit is therefore desired that the present embodiment be considered in allrespects as illustrative and not restrictive, reference being made tothe appended claims rather than to the foregoing description to indicatethe scope of the invention.

What is claimed:
 1. A method of manufacturing an interconnect for amagnetoresistive memory on a semiconductor substrate comprising thesteps of: (a) forming an initial dielectric layer overlying thesemiconductor substrate; (b) planarizing the initial dielectric layer;(c) forming a magnetoresistive storage layer overlying the initialdielectric layer; (d) forming an electrically-conductive initial stoplayer overlying the magnetoresistive storage layer; (e) forming anelectrically-conductive final stop layer overlying the initial stoplayer; (f) forming a hardmask layer overlying the final stop layer; (g)etching the hardmask layer and the final stop layer until the initialstop layer is exposed to define an etch region; (h) etching through theinitial stop layer and the magnetoresistive storage layer until theinitial dielectric layer is exposed using the etch region as an etchopening; (i) forming an isolation layer extending over the hardmasklayer and into the etch region, the isolation layer having sufficientthickness to fill in the gaps created by etching the etch region; (j)planarizing the isolation layer until regions of the final stop layerare exposed; and (k) forming an interconnect layer over the exposedregions of the final stop layer.
 2. The method of claim 1 wherein thestep of forming the initial dielectric layer comprises forming a layerof silicon nitride.
 3. The method of claim 1 wherein the step ofplanarizing the initial dielectric layer is completed using a chemicalmechanical polish.
 4. The method of claim 1 wherein the step of formingthe magnetoresistive storage layer comprises forming a plurality oflayers selected from the group consisting of cobalt, copper, nickel,iron, tantalum, and combinations thereof.
 5. The method of claim 1wherein the step of forming the initial stop layer comprises forming alayer having an etch selectivity which is greater than the etchselectivity of the hardmask layer.
 6. The method of claim 5 wherein thestep of forming the initial stop layer comprises forming a layer havingan etch selectivity which is 25 times greater than the etch selectivityof the hardmask layer.
 7. The method of claim 1 wherein the step offorming the initial stop layer comprises forming a layer consisting ofchromium and silicon.
 8. The method of claim 1 wherein the step offorming the final stop layer comprises forming a layer which has achemical mechanical polish stop selectivity which is greater than thehardmask layer.
 9. The method of claim 1 wherein the step of forming thefinal stop layer comprises forming a layer consisting of titanium andtungsten.
 10. The method of claim 1 wherein the step of forming thehardmask layer comprises forming a layer consisting of silicon dioxide.11. The method of claim 1 wherein the step of etching through theinitial stop layer and the magnetoresistive storage layer is completedusing blanket ion milling.
 12. The method of claim 1 wherein the step ofetching the hardmask layer and the final stop layer until the initialstop layer is exposed is completed using a dry etch.
 13. The method ofclaim 1 wherein the step of forming the isolation layer comprises thesteps of: forming an barrier layer extending over the hardmask layer andinto the etch region to conformally overlie the hardmask layer and theexposed portions of the final stop layer, the initial stop layer, themagnetoresistive storage layer and the initial dielectric layer in theetch region; and forming a final dielectric layer over the barrier layerwherein the final dielectric layer has sufficient thickness to fill inthe gaps created by etching the etch region.
 14. The method of claim 1wherein the step of forming the barrier layer comprises forming a layerconsisting of silicon nitride.
 15. The method of claim 1 wherein thestep of planarizing the isolation layer is completed using a chemicalmechanical polish.
 16. The method of claim 1 wherein the step of formingthe interconnect layer comprises forming a layer consisting of titaniumand tungsten.
 17. A method of manufacturing an interconnect for amagnetoresistive memory array comprising the steps of: (a) providing asemiconductor substrate; (b) forming an initial dielectric layeroverlying the semiconductor substrate; (c) planarizing the initialdielectric layer; (d) forming a magnetoresistive storage layer overlyingthe initial dielectric layer; (e) forming an electrically-conductiveinitial stop layer overlying the magnetoresistive storage layer; (f)forming an electrically-conductive final stop layer overlying theinitial stop layer; (g) forming a hardmask layer overlying the finalstop layer; (h) etching portions of the hardmask layer and the finalstop layer until the initial stop layer is exposed to define a pluralityof etch regions; (i) forming a plurality of magnetoresistive memorystorage bits by etching through the initial stop layer and themagnetoresistive storage layer until the initial dielectric layer isexposed using the plurality of etch regions as etch openings; (j)forming an isolation layer extending over the hardmask layer and intothe plurality of etch regions, the isolation layer having sufficientthickness to fill in the gaps created by etching the plurality of etchregions; (k) planarizing the isolation layer until a plurality ofregions of the final stop layer are exposed; and (l) forming a pluralityof interconnects over portions of the plurality of regions of the finalstop layer to interconnect each one of the plurality of magnetoresistivememory storage bits to another one of the plurality of magnetoresistivememory storage bits.
 18. The method of claim 17 wherein the step offorming the initial dielectric layer comprises forming a layer ofsilicon nitride.
 19. The method of claim 17 wherein the step ofplanarizing the initial dielectric layer is completed using a chemicalmechanical polish.
 20. The method of claim 17 wherein the step offorming the magnetoresistive storage layer comprises forming a pluralityof layers selected from the group consisting of cobalt, copper, nickel,iron, tantalum, and combinations thereof.
 21. The method of claim 17wherein the step of forming the initial stop layer comprises forming alayer having an etch selectivity which is greater than the etchselectivity of the hardmask layer.
 22. The method of claim 21 whereinthe step of forming the initial stop layer comprises forming a layerhaving an etch selectivity which is 25 times greater than the etchselectivity of the hardmask layer.
 23. The method of claim 17 whereinthe step of forming the initial stop layer comprises forming a layerconsisting of chromium and silicon.
 24. The method of claim 17 whereinthe step of forming the final stop layer comprises forming a layer whichhas a chemical mechanical polish stop selectivity which is greater thanthe hardmask layer.
 25. The method of claim 17 wherein the step offorming the final stop layer comprises forming a layer consisting oftitanium and tungsten.
 26. The method of claim 17 wherein the step offorming the hardmask layer comprises forming a layer consisting ofsilicon dioxide.
 27. The method of claim 17 wherein the step ofpatterning a plurality of magnetoresistive memory storage bits byetching through the initial stop layer and the magnetoresistive storagelayer is completed using blanket ion milling.
 28. The method of claim 17wherein the step of etching the hardmask layer and the final stop layeruntil the initial stop layer is exposed is completed using a dry etch.29. The method of claim 17 wherein the step of forming the isolationlayer comprises the steps of: forming a barrier layer extending over thehardmask layer and into the plurality of etch regions to conformallyoverlie the hardmask layer and the exposed portions of the final stoplayer, the initial stop layer, the magnetoresistive storage layer andthe initial dielectric layer in the plurality of etch regions; andforming a final dielectric layer over the barrier layer wherein thefinal dielectric layer has sufficient thickness to fill in the gapscreated by etching the plurality of etch regions.
 30. The method ofclaim 29 wherein the step of forming the barrier layer comprises forminga layer consisting of silicon nitride.
 31. The method of claim 17wherein the step of planarizing the isolation layer is completed using achemical mechanical polish.
 32. The method of claim 17 wherein the stepof forming a plurality of interconnects over portions of the pluralityof regions of the final stop layer comprises the steps of: depositing alayer of interconnect metal which overlies the plurality of regions ofthe final stop layer; and selectively etching the layer of interconnectmetal to interconnect each one of the plurality of magnetoresistivememory storage bits to another one of the plurality of magnetoresistivememory storage bits.
 33. The method of claim 32 wherein the step ofdepositing a layer of interconnect metal comprises depositing a layerconsisting of titanium and tungsten.
 34. The method of claim 17 whereinthe step of providing a semiconductor substrate further comprises thestep of forming an initial layer of metal overlying the semiconductorsubstrate, the initial dielectric layer overlying the initial layer ofmetal.
 35. A method of manufacturing an interconnect for amagnetoresistive memory storage device having a plurality ofmagnetoresistive memory storage bits and read and write controlcircuitry for reading data from and writing data to the plurality ofmagnetoresistive memory storage bits, comprising the steps of: (a)providing a semiconductor substrate; (b) forming the read and writecontrol circuitry on the semiconductor substrate; (c) forming an initialdielectric layer overlying the read and write control circuitry; (d)planarizing the initial dielectric layer; (e) forming a magnetoresistivestorage layer overlying the initial dielectric layer; (f) forming anelectrically-conductive initial stop layer overlying themagnetoresistive storage layer; (g) forming an electrically-conductivefinal stop layer overlying the initial stop layer; (h) forming ahardmask layer overlying the final stop layer; (i) etching portions ofthe hardmask layer and the final stop layer until the initial stop layeris exposed to define a plurality of etch regions; (j) forming theplurality of magnetoresistive memory storage bits by etching through theinitial stop layer and the magnetoresistive storage layer until theinitial dielectric layer is exposed using the plurality of etch regionsas etch openings; forming an isolation layer extending over the hardmasklayer and into the plurality of etch regions, the isolation layer havingsufficient thickness to fill in the gaps created by etching theplurality of etch regions; (k) planarizing the isolation layer until aplurality of regions of the final stop layer are exposed; and (l)forming a plurality of interconnects over portions of the plurality ofregions of the final stop layer to interconnect each one of theplurality of magnetoresistive memory storage bits to another one of theplurality of magnetoresistive memory storage bits.
 36. The method ofclaim 35 wherein the step of forming the initial dielectric layercomprises forming a layer of silicon nitride.
 37. The method of claim 35wherein the step of planarizing the initial dielectric layer iscompleted using a chemical mechanical polish.
 38. The method of claim 35wherein the step of forming the magnetoresistive storage layer comprisesforming a plurality of layers selected from the group consisting ofcobalt, copper, nickel, iron, tantalum, and combinations thereof. 39.The method of claim 35 wherein the step of forming the initial stoplayer comprises forming a layer having an etch selectivity which isgreater than the etch selectivity of the hardmask layer.
 40. The methodof claim 39 wherein the step of forming the initial stop layer comprisesforming a layer having an etch selectivity which is 25 times greaterthan the etch selectivity of the hardmask layer.
 41. The method of claim35 wherein the step of forming the initial stop layer comprises forminga layer consisting of chromium and silicon.
 42. The method of claim 35wherein the step of forming the final stop layer comprises forming alayer which has a chemical mechanical polish stop selectivity which isgreater than the hardmask layer.
 43. The method of claim 35 wherein thestep of forming the final stop layer comprises forming a layerconsisting of titanium and tungsten.
 44. The method of claim 35 whereinthe step of forming the hardmask layer comprises forming a layerconsisting of silicon dioxide.
 45. The method of claim 35 wherein thestep of patterning a plurality of magnetoresistive memory storage bitsby etching through the initial stop layer and the magnetoresistivestorage layer is completed using blanket ion milling.
 46. The method ofclaim 35 wherein the step of etching the hardmask layer and the finalstop layer until the initial stop layer is exposed is completed using adry etch.
 47. The method of claim 35 wherein the step of forming theisolation layer comprises the steps of: forming a barrier layerextending over the hardmask layer and into the plurality of etch regionsto conformally overlie the hardmask layer and the exposed portions ofthe final stop layer, the initial stop layer, the magnetoresistivestorage layer and the initial dielectric layer in the plurality of etchregions; and forming a final dielectric layer over the barrier layerwherein the final dielectric layer has sufficient thickness to fill inthe gaps created by etching the plurality of etch regions.
 48. Themethod of claim 47 wherein the step of forming the barrier layercomprises forming a layer consisting of silicon nitride.
 49. The methodof claim 35 wherein the step of planarizing the isolation layer iscompleted using a chemical mechanical polish.
 50. The method of claim 35wherein the step of forming a plurality of interconnects over portionsof the plurality of regions of the final stop layer comprises the stepsof: depositing a layer of interconnect metal which overlies theplurality of regions of the final stop layer; and selectively etchingthe layer of interconnect metal to interconnect each one of theplurality of magnetoresistive memory storage bits to another one of theplurality of magnetoresistive memory storage bits.
 51. The method ofclaim 50 wherein the step of depositing a layer of interconnect metalcomprises depositing a layer consisting of titanium and tungsten. 52.The method of claim 35 wherein the step of forming the read and writecontrol circuitry on the semiconductor substrate comprises using acomplementary metal-oxide semiconductor process.
 53. The method of claim35 wherein the step of providing a semiconductor substrate furthercomprises the step of forming an initial layer of metal overlying thesemiconductor substrate, the initial dielectric layer overlying theinitial layer of metal.
 54. A method of manufacturing an interconnectfor a magnetoresistive memory on a semiconductor substrate comprisingthe steps of: (a) forming an initial dielectric layer overlying thesemiconductor substrate; (b) planarizing the initial dielectric layer;(c) forming a magnetoresistive storage layer overlying the initialdielectric layer; (d) forming an electrically-conductive stop layeroverlying the magnetoresistive storage layer; (e) forming a hardmasklayer overlying the stop layer; (f) etching the hardmask layer until thestop layer is exposed to define an etch region; (g) etching through thestop layer and the magnetoresistive storage layer until the initialdielectric layer is exposed using the etch region as an etch opening;forming an isolation layer extending over the hardmask layer and intothe etch region, the isolation layer having sufficient thickness to fillin the gaps created by etching the etch region; (h) planarizing theisolation layer until regions of the stop layer are exposed; and formingan interconnect layer over the exposed regions of the stop layer. 55.The method of claim 54, further comprising the step of: forming a secondelectrically-conductive stop layer over the stop layer; and wherein thestep of etching through the hardmask layer includes etching through thesecond stop layer.
 56. A method of manufacturing an interconnect for amagnetoresistive memory on a semiconductor substrate comprising thesteps of: (a) forming an initial dielectric layer overlying thesemiconductor substrate; (b) planarizing the initial dielectric layer;(c) forming a magnetoresistive storage layer overlying the initialdielectric layer; (d) forming an electrically conductive stop layeroverlying the magnetoresistive storage layer; (e) forming a hardmasklayer overlying the stop layer, the hardmask layer having an etchselectivity less than the etch selectivity of the stop layer; (f)etching the hardmask layer until the stop layer is exposed to define anetch region; (g) etching through the stop layer and the magnetoresistivestorage layer using blanket ion milling until the initial dielectriclayer is exposed using the etch region as an etch opening; (h) formingan isolation layer extending over the hardmask layer and into the etchregion, the isolation layer having sufficient thickness to fill in thegaps created by etching the etch region; (i) planarizing the isolationlayer using chemical mechanical polishing until regions of the stoplayer are exposed; and (j) forming an interconnect layer over theexposed regions of the stop layer.
 57. The method of claim 56, furthercomprising the step of: forming a second electrically conductive stoplayer over the stop layer; and wherein the step of etching through thehardmask layer includes etching through the second stop layer.
 58. Themethod of claim 57 wherein the step of forming the second stop layercomprises forming a layer which has a chemical mechanical polish stopselectivity which is greater than the hardmask layer.
 59. A method offorming a high current, electromigration-resistant metal interconnectbetween circuit elements on a semiconductor substrate, comprising thesteps of: (a) forming a non-conducting layer over the semiconductorsubstrate; (b) planarizing the non-conducting layer; (c) forming acircuit element layer over the non-conducting layer; (d) forming anelectrically-conducting stop layer over the circuit element layer; (e)forming a hardmask layer over the stop layer; (f) etching the hardmasklayer to expose the stop layer to define an etch region; (g) etchingthrough the stop layer and the circuit element layer until thenon-conducting layer is exposed using the etch region as an etchopening; (h) forming an isolation layer extending over the hardmasklayer and into the etch region, the isolation layer having sufficientthickness to fill in the gaps created by etching the etch region; (i)planarizing the isolation layer until regions of the stop layer areexposed; and forming an interconnect layer over the exposed regions ofthe stop layer.
 60. The method of claim 59, further comprising the stepof: forming a second electrically conductive stop layer over the stoplayer; and wherein the step of etching through the hardmask layerincludes etching through the second stop layer.
 61. The method of claim60 wherein the step of forming the second stop layer comprises forming alayer which has a chemical mechanical polish stop selectivity which isgreater than the hardmask layer.